Where a scalar processor would have to perform a load, an addition and a store instruction for every element, a vector processor performs one load, one addition and one store for multiple elements. The need for using vector instructions cannot be understated, as it is the key to efficiently utilizing the VPUs for high performance.įigure 1: Illustration of SIMD instructionįigure 1 shows an example of a vector instruction adding multiple numbers together at the same time, compared to doing the additions sequentially. Each VPU operates independently on 512-bit vector registers, which can hold 16 single precision or 8 double precision floating-point numbers. This performance gain is partly due to the presence of two vector processing units (VPUs) per core, doubled compared to the previous generation. The Knights Landing architecture has a peak theoretical performance of 6 TFLOP/s in single precision, which is triple than what Knights Corner had. 2nd generation Intel Xeon Phi processors, to be released in 2016 and code-named Knights Landing (KNL), also support 512-bit vectors, but in a new instruction set called Intel® Advanced Vector Extensions 512 (Intel® AVX-512). 1st generation Intel Xeon Phi processors, released in 2012 and code-named Knights Corner (KNC), were first Intel architecture processors to support 512-bit vectors. Data parallelism comes from support for vector instructions, which make every core a single instruction multiple data (SIMD) processor. Task parallelism comes from the massive number of cores in the processor (up to 72). Parallelism is present in these processors at two levels: task parallelism and data parallelism. Intel® Xeon Phi™products are highly parallel processors with the Intel® Many Integrated Core (MIC) architecture.

Intel c compiler flag list -c++